Vista offers top-down modeling, a set of key architecture blocks that can be easily configured, an intuitive graphical assembly platform, and a hardware/software debug and analysis toolset.

The models constructing the system can be intuitively set to various micro-architecture configurations, interconnect layering, and memory hierarchies. The unique layered timing approach offered by Vista enables users to quickly test various configurations using powerful timing policies while keeping functionality intact.

Users can exercise statistical and randomized data traffic simulation or software-driven simulation with a target processor.

Vista has a powerful analysis toolset for intuitively viewing and analyzing different performance and power metrics, as well as for observing load peaks, average latencies, throughput, and utilization on any port, bus, or sub-system.

With Vista, users can rapidly prototype systems using the key hardware blocks and analyze power and performance under different scenarios and traffic loads. The scalable modeling approach supported in Vista enables design teams to manage timing and power from system concept to the desired implementation.

Features：

• Set of configurable TLM 2.0-based architecture blocks: CPU, BUS (AXI, AHB), Memory, Cache, DMAC, INTC, and others
• Statistical and functional up-front modeling utilities
• Tracing of data packets and model states and attributes
• TLM 2.0 graphical assembly
• Integrated HW/SW platform with target processors and SW tools
• Advanced SystemC and TLM 2.0 debug and tracing
• Advanced analysis and visualization tools and reports
• Analyze power, throughput, latencies, utilization, and states