HDL Author

Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.

Standard languages (such as VHDL, Verilog, SystemVerilog) and IP formats, along with common industry version management systems aid in producing repeatable and dependable design processes, but the tools that utilize these standards need to do much more than edit text files. Mentor Graphics delivers a complete design solution for FPGA and ASIC HDL development beginning with comprehensive design creation addressing new code creation, formal and informal design reuse, and any combination in between.

KEY FEATURES & BENEFITS:

Physical Synthesis

• Performs optimizations using post-P&R data
• Reduces runtime of future P&R iterations

Interactive Physical Layout Editor

• Find trouble areas in physical implementation
• Optimize specific areas or timing paths

Modular Design Reuse Flow

• Reuses placement of unmodified blocks

Enhanced Design Analysis

• Cross-probe between design schematics and physical layout

All Features of Precision RTL Plus

• Mil-aero & safety-critical features
• Physical synthesis (pre-P&R)
• Low power synthesis
• Incremental flows
• Precise-IP
• Precise-Encrypt
• Mixed language support with SystemVerilog
• Resource Manager
• ASIC prototyping support
• Integration with Mentor tools