Visual Elite offers a variety of languages and design entry methods allowing the user to select the best suited approach for their modeling needs. Visual Elite supports both text-based and graphical entry, including block diagrams, state diagrams and connectivity tables. Designers can use VHDL, Verilog, SystemC or any combination of these to design and build products.

Visual Elite allows distributed design teams efficient control and management of the entire design process. Built-in documentation and reuse features, such as text-to-graphics transformation, simplify design management. The design infrastructure for data and project management enables team leaders to enforce a consistent design flow and methodology. The documentation capability enables chip architects and designers to share ideas and design requirements, including hierarchical views within HTML, and links into Microsoft OLE and FrameMaker.

Visual Elite can link with existing mixed-language designs and offer cross language model distribution, including mapping SystemC RTL into HDL. Model generation can be tailored to various SystemC and HDL synthesis tools and allows single source modeling. Visual Elite supports custom modules from tools such as SPW, Matlab, and popular FPGA core libraries.

FEATURES AND BENEFITS：

• Mix and match different levels of abstractions
• Native language front-end eases learning curve and adoption
• Intuitive design methods allow design sharing and reuse
• Improves revision control tracking and documentation
• Links with Vista, Questa and other mixed language simulators

• SystemC and HDL Mixed language design and integration
• Variety of text and graphical design creation methods
• Cross language code generation
• Unique macro set for SystemC and HDL data flow design
• Automatically maps source code into graphical representation